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| PRODUCT Single channel T3/E3 Framer & Line Interface for ATM, Frame Relay and PPP/IP. The TE3-FALC(R) is a complete solution for a T3/E3 broadband interface. It includes DS3/E3 framing, analog line interface, two jitter attenuators and the mapping of ATM or PPP/HDLC. The TE3-FALC(R) also integrates a microcontroller which is running the device driver and gathering statistics as managed MIB objects. On the line side the TE3-FALC(R) interfaces to a 75 co-axial cable via transformers. Highly accurate analog pulse shaping removes the need to measure cable length and set the Line Build Out. On the system side, industry standard UTOPIA and POS-PHY interface as well as a serial clock/data port are provided. This allows the TE3-FALC(R) to be connected to a wide array of Layer 2/3 & 4 network processors. BRIEF Applications s Wireless base stations s LAN/WAN router s DSLAMs s Remote access/concentrator s Multimedia gateways Analog Line Interface Single channel T3/E3 analog receive & transmit circuitry s Identical T3/E3 transformer interface. True software switchable s Clock & data recovery s Analog LOS detection s Single pulse template for all line length 0 - 450 ft, no need for setting of Line Build Out s DS3/E3 Framer s E3 Framer supporting G.832, G.751 & TBR24 s DS3 framer supporting M23 and C-Bit parity modes s Processing of all DS3 overhead channels including the FEAC and MDL link s Processing of all E3 overhead channels such as trail trace s PLCP sub frame for DS3/E3 G.751 allowing the mapping of ATM cells s DS3/E3 BERT unit ATM Cell Processor Cell processor as per G.804 s Mapping cells directly into DS3/E3 frames or via PLCP frame s TE3-FALC Test and Diagnostic s JTAG test port s OCDS debug port s (R) Embedded Controller Embedded microcontroller with all code & data memory General Features 3.3 V I/O CMOS technology s 1.8 V core logic supply s P-BGA-272 package 27 x 27 mm body size, 1.27 mm ball pitch s Industrial temperature range package, -40 C to +85 C s Digital Jitter Attenuator Two separate transmit and receive jitter attenuators s Meets jitter transfer requirements s All line rate clocks generated internally, no requirement for external 34/45 MHz oscillators s Clock generation unit accepts flexible frequency reference clocks, 4 MHz to 52 MHz s PPP Processor Bit and byte synchronous HDLC controller s Generation and detection of flags, bit stuffing, CRC-16/32 s System Interfaces Utopia Level 2 interface 8/16 Bit s POS-PHY interface 8/16 Bit s Serial clock and data interface s 8/16 Bit Motorola/Intel processor interface s Key Features Integrated T3/E3 analog s Single pulse template for all line lengths, no LBO requirement s Jitter attenuation in both Tx and Rx s Full featured DS3/E3 framer s ATM and PPP/HDLC mapping s UTOPIA or POS-PHY interface s Integrated C running S/W driver s Control via 8/16 Bit Motorola/Intel P i/f or inband ATM/PPP messages s High level message based API s T E 3 - F A L C(R) PEF 3460E www.infineon.com Never stop thinking. PRODUCT TE3-FALC(R) PEF 3460E Block Diagram Bitstream/Overhead Access Interface Tx Line Interface Analog or Digital T3/E3 LIU ATM Cell Processor G.804 Direct Mapping PLCP Mapping HDLC Packet Processor Bit-synchronous PPP Octet-synchronous PPP Boot ROM Control JTAG TEST BRIEF Transmit DJAT DS3/E3 Framer DS3 C-Bit Parity/M23 E3 G.832/G.751 FDL Insert DS3 FEAC DS3 MDL, E3 TTI Transmit Insert Transmit Filter & Extract Transmit System Interface UTOPIA UTOPIA-L2X POS-PHY BERT Microcontroller Core with Memory P Interface Clock Multiplier PLL FDL Extract DS3 FEAC DS3 MDL, E3 TTI BERT HDLC Packet Processor Bit-synchronous PPP Octet-synchronous PPP ATM Cell Processor G.804 Direct Demapping PLCP Demapping T3/E3 LIU Rx Line Interface Analog or Digital Receive DJAT DS3/E3 Deframer DS3 C-Bit Parity/M23 E3 G.832/G.751 Bitstream/Overhead Access Interface Receive Filter & Extract Receive Insert Receive System Interface UTOPIA UTOPIA-L2X POS-PHY UART General Purpose I/O Port TE3-FALC(R) PEF 3460E Application Examples Comparison with existing single channel solution UTOPIA UTOPIA -L2X POS-PHY TE3-FALC(R) 45 MHz Osc. 34 MHz Osc. HDLC/POS FPGA T3/E3 Framer + ATM TC Jitter Attenuator T3/E3 LIU 4 Wire PLL for Control 34/45 MHz 8/16 Bit Micro Interface 4 Wire Control FPGA Status & Control Red LED (LOS, LOF, AIS & LCD) Yellow LED (RDI) Documentation and Support Package s Product overview s Product Data Sheet s Firmware Brief s Application Notes s Evaluation Tool EASY3460 s Configuration Assistant s IBIS Model s BSDL File Infineon Companion Products FALC(R) 56: PEB 2256 TM s QuadFALC : PEB 22554 TM s QuadLIU : PEB 22504 TM s TE3-LIU : PEB 3452 TM s TE3-MUX : PEB 3445 s DSCC4: PEB 20534 s TE3-CHATT: PEB 3456 s ALP: PXB 4350 s AOP: PXB 4340 s ABM: PXB 4330 s IWE8: PXB 4220/4221 s IWORX: PXB 4225 s ATM, FR or IP/PPP over T3/E3 STCLK STD[15:0] STSX STENB RL2 STPA STADDR[4:0] STPRTY TE3-FALC(R) SRCLK XL1 SRD[15:0] SRSX SRPA XL2 SRENB SRADDR[4:0] SRPRTY RL1 TxCLK TxDATA[15:0] TxSOC TxENB TxCLAV TxADDR[4:0] TxPRTY RxCLK RxDATA[15:0] RxSOC RxCLAV RxENB RxADDR[4:0] RxPRTY ATM Layer or N/W P Infineon ALP (PXB 4350) Other ATM Layer or NPU Solutions How to reach us: http://www.infineon.com Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81541 Munchen (c) Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in lifesupport devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Ordering No. B119-H7761-G1-X-7600 Printed in Germany PS 11015. NB Published by Infineon Technologies AG |
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